Vedad Hadžić

Dipl.-Ing. BSc

Formal Methods, Research Staff

Vedad Hadžić officially joined IAIK as a PhD Student in December 2019, but was already an active student research collaborator since 2016. In November 2022 he completed his PhD Proposal Defense and became a PhD Candidate. The main focus of his research is the design and formal verification of side-channel resistant implementations in hardware. This puts him right at the crossover between the Secure Systems and Formal Methods groups at IAIK, which led to several inter-group collaborations on formal side-channel analysis, fault-attack analysis and memory-safety formalization.
+43 316 873 - 5579
vedad.hadzic@tugraz.at
https://www.iaik.tugraz.at
IF02024
TUGRAZ online
Vedad Hadžić

Publications

Cryptographic Least Privilege Enforcement for Scalable Memory Isolation

Unterguggenberger M., Schrammel D., Maar L., Lamster L., Hadzic V., Mangard S.
IEEE International Symposium on Hardware Oriented Security and Trust (HOST), IEEE International Symposium on Hardware Oriented Security and Trust 2025: HOST 2025

Efficient and Composable Masked AES S-Box Designs Using Optimized Inverters

Hadzic V., Bloem R.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025(1), 656-683

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Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults

Tollec S., Hadzic V., Nasahl P., Asavoae M., Bloem R., Couroussé D., Heydemann K., Jan M., Mangard S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2024(4), 179-204

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Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

Haring J., Hadzic V., Bloem R.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2024(4), 110-132

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Quantile: Quantifying Information Leakage

Hadzic V., Cassiers G., Primas R., Mangard S., Bloem R.

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