Digital System Design (SS 2025)
Table of Content
Content
The goal of the course Digital System Design is to teach the central aspects of designing digital integrated circuits by a systematic approach and methodology. The course covers the whole spectrum of the design: it starts with specifications on system-level and ends at the generation and verification of layout masks, which are needed for production. The content offered in the lectures is accompanied by an exercise (KU) where participants have the chance to put the knowledge into practice by using the latest professional design tools as they are used in the semiconductor industry.
The practicals of Digital System Design cover the design of a digital integrated circuit. During the work the following tasks have to be accomplished:
- System-level specification
- Algorithmic evaluation
- Architectural choices
- Register-level transfer modeling (VHDL, Verilog, SystemVerilog)
- Dynamic functional verification (HDL simulation)
- Synthesis
- Place & Route
- Back-end verification
The practical work is committed with either open-source tools (OpenROAD, Caravel Harness SoC) or professional CAD tools from Cadence. The outcome of the lab is the layout of a CMOS circuit that is nearly suitable for tape-out (production).
You can find last year's DSD course here: SS2024
Material
| Topic | Slides |
|---|---|
| 01 Introduction & Motivation | 01_Introduction |
| 02 Digital Design Flow | Cipher Spec | 02_Design_Flow | Cipher_Specification |
| 03 Architecture Design Example | 03 Design_ofDesign_study_AES_AES |
| 04 Data and Control Flow Graphs | 04_SDFG_and_CFG |
| 05 Architecture Transformation | 05_ Architecture_Transformation |
| 06 - | |
| 07 - | |
| 08 - | |
| 09 - | |
| 10 - | |
| 11 - | |
| 12 - |
Administrative Information
Lecture
Exam. There is one written exam at the end of the semester. An additional exam date is planned for the end of September. Other exam dates are offered on request.Practicals
Practicals: In the lab practicals, students design an integrated digital circuit that implements a cryptographic algorithm. By applying a hierarchical structuring of the circuit, many principles of digital system design become clear. The lab centers on the description of circuits using hardware-description languages but it also covers algorithmic improvements and optimizations on circuit level.
Groups. The Digital System Design KU is done in groups of two. Look out for a group early.
Computers, Accounts, Software, Design flow. We provide a docker container that contains all required tools for the practicals. In addition, for the duration of the practicals, participants can obtain access to the research cluster located at ISEC via a StudentNet account. This allows you to work with industry tools.
Discord. Discussions with other students are possible in the #dsd-questions channel in Discord.
Exams. The practicals is a team work of two students. The course consists of multiple assignments with separate submisison dates. The final submission of deliverables is graded during a colloquium / discussion.
| Topic | Download |
|---|---|
| Cadence Software Usage Agreement | Download |
| Design Document Draft | Download |
| SystemVerilog Tutorial (Legacy) | Download |
| IAIK-Open-Flow Presentation | Download |
| IAIK-Closed-Flow Presentation | |
| Assignment Sheet | Download |
| Assignment 1 presentation | Slides |
| Assignment 2 presentation |
Lecture Dates
| Date | Begin | End | Location | Event | Type | Comment |
|---|---|---|---|---|---|---|
| 2025/04/08 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/04/29 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/04/29 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/05/06 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/05/13 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/05/20 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/05/27 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/06/03 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/06/17 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
| 2025/06/24 | 10:00 | 11:30 | HS i3 "LENZING Hörsaal" | Abhaltung | VO | fix/ |
